As integrated circuits become increasingly smaller and more complex, it has become necessary to create multiple layers of conductive interconnections between transistors. These conductive interconnections are often, although not necessarily, made from metal and are termed "runners."
In a typical Field Effect Transistor (FET) integrated circuit fabrication process, the source, drain and gate are formed first. Then a layer of dielectric material is formed to cover the source, drain and gate. The dielectric is subsequently patterned to create openings, often termed "windows" or "vias" over transistor regions (such as the source, drain or gate) to which an electrical contact is desired. For convenience and simplicity, dielectric openings will be termed "vias" in the following paragraphs. In typical subsequent processing, a conductive material may be deposited both in the vias and as a blanket layer upon the dielectric.
In certain integrated circuit designs, the vias may be filled utilizing the same process which forms the blanket metallic layer. In other designs, a conductive plug may be formed within the via and then the overlying blanket metallic layer may be formed in a separate step. In certain designs, the plug may be made of a different material from the overlying blanket metallic layer. In other designs, the plug and the overlying metallic layer may be made of the same material. After the blanket metallic layer has been formed, the blanket layer is patterned to form runners which may connect individual transistors.
When the plug and the overlying blanket layer are formed from the same material, various problems may arise during subsequent processing. For example, there is a danger that a misalignment of the runner mask will permit the runner etching process to expose a portion of the upper surface of the plug and etch the plug (at least in the vicinity of the via wall), thereby damaging it.
One solution to the misalignment problem is to employ "nailheads." Nailheads are portions of increased width within a runner. Nailheads are dimensioned and positioned within the runner to completely cover a plug even if a mask misalignment should occur. Thus, if the protective nailhead is properly positioned, a slight misalignment of the runner mask will not pose any danger to the underlying plug because the plug will remain covered by the nailhead during the runner etching process. However, one disadvantage to the use of nailheads is that they consume extra space in the circuit layout. As integrated circuit geometrics shrink, designers have consistently sought ways to reduce space consumption.
In more complex integrated circuits, additional layers of conductive interconnection may be fabricated by a repetition of the process described above. For example, a second layer of dielectric material may be formed which covers both the previously formed runners and the first dielectric layer upon which those runners are formed. Then vias may be opened in the second dielectric layer. The vias may be filled with conductive material and an overlying blanket metallic layer may then be patterned to form a higher level runner. The higher level runners electrically connect the lower level runners through the vias.
The next few paragraphs discuss some of the more commonly used interconnection materials. Sputtered aluminum is a commonly used material for forming conductive interconnections. However, the use of aluminum presents certain problems to the integrated circuit designer. Sputtered aluminum generally exhibits poor step coverage in vias and does not fill them adequately. Special procedures or techniques must often be employed to create aluminum plugs which will adequately fill vias. Furthermore, aluminum does not tolerate high temperature processing very well. Consequently, after aluminum runners have been formed, subsequent thermal processing of the integrated circuit must be restricted to low temperatures.
Tungsten has become an increasingly popular material for integrated circuit fabrication. Tungsten plugs may be formed within high aspect ratio vias by techniques known to those skilled in the art. Often a tungsten plug is formed by etching back a blanket tungsten layer. A disadvantage is that the blanket tungsten, which fills the vias somewhat conformally, often exhibits a central seam in the via and/or a dimple on top of the via. The seam is particularly vulnerable to the etching process used to form the plugs. Thus, the process of forming the plugs from blanket tungsten may destroy or at least impair the tungsten material within the via. The tungsten plug is frequently contacted by an overlying aluminum blanket layer. The aluminum layer is subsequently patterned to form runners. However, as mentioned before, the presence of the aluminum runners means that subsequent thermal processing must be restricted to lower temperatures. Another disadvantage is that aluminum and tungsten may react to form an intermetallic compound.
Integrated circuits designers have given increasing attention to the use of tungsten as an interconnection material, i.e., as a runner. The conductive tungsten runners are comparatively impervious to subsequent routine high temperature processing. For example, after vias are defined, a blanket layer of tungsten is deposited, which both fills the vias and covers the dielectric. Then the tungsten is patterned to form runners. However, the use of blanket tungsten to both fill vias and form runners may have disadvantages. One disadvantage of the blanket tungsten approach is that adhesion between the tungsten and underlying dielectric is often poor. Also, the process for etching tungsten to form runners can result in an etch down the plugs if the photoresist is misaligned.